1. Field of the Invention
The present invention relates generally to a DRAM cell structure and more particularly to a stacked capacitor (STC) DRAM cell.
2. Description of the Related Art
In order to increase the integration density in DRAM cell arrangements, DRAM cells are optimized to a reduced space requirement, on the one hand, and the arrangement of the DRAM cells relative to one another in a DRAM cell arrangement is optimized on the other hand.
A DRAM cell having a reduced space requirement is the so-called stacked-capacitor DRAM cell. It comprises an MOS transistor and a storage capacitor, the MOS transistor being arranged in a silicon substrate and the storage capacitor comprising two doped polysilicon layers and a dielectric layer arranged therebetween, which are arranged on the surface of the substrate. In this case, the storage capacitor covers entirely or partially that area which is occupied by the transistor. The MOS transistor is referred to as a cell transistor.
A further reduction in the space requirement is achieved in the stacked-capacitor DRAM cell owing to the fact that the storage capacitor is arranged above a bitline. This variant of the stacked-capacitor DRAM cell is referred to as a buried-bitline-stacked-capacitor (BBSTC) DRAM cell. In this case, it is necessary to produce a connection between the MOS transistor and the storage node of the storage capacitor, that is to say that electrode of the storage capacitor on which the information is stored. Such a connection is referred to as a cell contact.
The arrangement of the cells is also interrelated with the circuitry for their activation. In order to read out the stored information, a wordline is activated, as a result of which all the transistors located on this line become conductive and thus cause the stored charges to flow off to an assigned bitline in each case. Subsequently, the voltages of two bitlines are compared in a read amplifier. The one bitline represents in this case the connection from the cell to be evaluated to the read amplifier, while no cell is permitted to be active at the other bitline for the time being (the second bitline is thus termed reference bitline). The first bitline is referred to as the addressed bitline; it is connected to a cell transistor whose gate is formed by the activated wordline. The reference bitline is also referred to as non-addressed. If the addressed and non-addressed bitlines are always located alternately next to one another, a pair of adjacent bitlines can be evaluated in each case by a read amplifier. This cell arrangement is referred to as a folded bitline.
S. Kimura et al, IEDM'88, pages 596 ff and S. Kimura et al, IEEE Trans. Elect. Dev., volume 37 (1990), pages 737 ff disclose a BBSTC-DRAM cell in which the channel area and source of the cell transistors extend at an angle of approximately 45.degree. to the wordlines and the bitlines. The wordlines and the bitlines are arranged in this case at right angles to one another. The active areas are bent between the drain area and channel area. It is possible thereby for cell contacts to be opened during manufacture with the aid of a spacer technique in a self-adjusted fashion through the wordline and the bitline plane onto an n.sup.+ -doped area which merges, or extends into the drain area of the cell transistor. The storage node is produced in an overlapping manner relative to this cell contact.
The known cell arrangement is a folded-bitline arrangement. The cell contacts are located relatively close to one another in this case. By contrast, the bitline contacts, which reach up to the source areas of the MOS transistors, are relatively far removed from one another because of the bent course of the active area. This results in the active areas being relatively closely spaced in the plane and only being separated from one another by field isolation, on the one hand, while, on the other hand, relatively large areas go unused.